Method of a driving plasma display panel

ABSTRACT

A method of driving a plasma display panel having front and rear substrates opposed to and facing each other, X and Y electrode lines formed between the front and rear substrates to be parallel to each other, address electrode lines formed to be orthogonal to the X and Y electrode lines, to define corresponding pixels at interconnections, and the address electrode lines are cut into two parts at the middle portions thereof to then form first and second panels separately driven such that the minimum driving period includes a display discharge period, a reset period and an address period, a scan pulse is applied to at least one of the respective Y electrode lines during the address period and the corresponding display data signals are simultaneously applied to the respective address electrode lines to form wall charges at pixels to be displayed, pulses for a display discharge are alternately applied to the X and Y electrode lines to cause a display discharge at the pixels where the wall charges have been formed, and a reset pulse for forming space charges while erasing the wall charges remaining from the previous subfield is applied to the corresponding Y electrode lines during the reset period, wherein the address period is applied to the second panel while the display discharge period and the reset period are applied to the first panel.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of Korean Application No.99-56558, filed Dec. 10, 1999, in the Korean Patent Office, thedisclosure of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a method of driving a plasmadisplay panel, and more particularly, to a method of driving athree-electrode surface-discharge plasma display panel.

[0004] 2. Description of the Related Art

[0005]FIG. 1 shows a structure of a general three-electrodesurface-discharge plasma display panel, FIG. 2 shows an electrode linepattern of the panel shown in FIG. 1, and FIG. 3 shows an example of apixel of the panel shown in FIG. 1. Referring to the drawings, addresselectrode lines A₁, A₂, . . . A_(m), dielectric layers 11 and 15, Yelectrode lines Y₁, . Y₂, . . . Y_(n), X electrode lines X₁, X₂, . . .X_(n), phosphors 16, partition walls 17 and an MgO protective film 12are provided between front and rear glass substrates 10 and 13 of ageneral surface-discharge plasma display panel 1.

[0006] The address electrode lines A₁, A₂, . . . A_(m) are provided overthe front surface of the rear glass substrate 13 in a predeterminedpattern. The lower dielectric layer 15 covers the entire front surfaceof the address electrode lines A₁, A₂, . . . A_(m). The partition walls17 are formed on the front surface of the lower dielectric layer 15 tobe parallel to the address electrode lines A₁, A₂, . . . A_(m). Thepartition walls 17 define discharge areas of the respective pixels andprevent optical crosstalk among pixels. The phosphors 16 are coatedbetween partition walls 17.

[0007] The X electrode lines X₁, X₂, . . . X_(n) and the Y electrodelines Y₁, Y₂, . . . Y_(n) are arranged on the rear surface of the frontglass substrate 10 so as to be orthogonal to the address electrode linesA₁, A₂, . . . A_(m), in a predetermined pattern. The respectiveintersections define corresponding pixels. Each of the X electrode linesX₁, X₂, . . . X_(n) and the Y electrode lines Y₁, . Y₂ . . . Y_(n)comprises a transparent, conductive indium tin oxide (ITO) electrodeline (X_(na) or Y_(na) of FIG. 3) and a metal bus electrode line (X_(nb)or Y_(nb) of FIG. 3). The upper dielectric layer 11 is entirely coatedover the rear surfaces of the X electrode lines X₁, X₂, . . . X_(n) andthe Y electrode lines Y₁, . Y₂, . . . Y_(n). The MgO protective film 12for protecting the plasma display panel 1 against strong electricalfields is entirely coated over the rear surface of the upper dielectriclayer 11. A gas for forming plasma is hermetically sealed in a dischargespace 14.

[0008] The above-described plasma display panel 1 is basically drivensuch that a reset step, an address step and a sustain-discharge step aresequentially performed in a unit subfield. In the reset step, wallcharges remaining from the previous subfield are erased and spacecharges are evenly formed. In the address step, the wall charges areformed in a selected pixel area. Also, in the sustain-discharge step,light is produced at the pixel at which the wall charges are formed inthe address step. In other words, if alternating pulses of a relativelyhigh voltage are applied between the X electrode lines X₁, X₂, . . .X_(n) and the corresponding Y electrode lines Y₁, Y₂, . . . Y_(n), asurface discharge occurs at the pixels at which the wall charges areformed. Here, plasma is formed at the gas layer of the discharge space14 and phosphors 16 are excited by ultraviolet rays to thus emit light.

[0009]FIG. 4 shows the structure of a unit display period based on adriving method of a general plasma display panel. Here, a unit displayperiod represents a frame in the case of a progressive scanning method,and a field in the case of an interlaced scanning method. The drivingmethod shown in FIG. 4 is generally referred to as a multiple addressoverlapping display driving method. According to this driving method,pulses for a display discharge are consistently applied to all Xelectrode lines (X₁, X₂, . . . X_(n) of FIG. 1) and all Y electrodelines (Y₁, Y₂, . . . Y₄₈₀) and pulses for resetting or addressing areapplied between the respective pulses for a display discharge. In otherwords, the reset and address steps are sequentially performed withrespect to individual Y electrode lines or groups, within a unitsub-field, and then the display discharge step is performed for theremaining time period. Thus, compared to an address-display separationdriving method, the multiple address overlapping display driving methodhas an enhanced displayed luminance. Here, the address-displayseparation driving method refers to a method in which within a unitsubfield, reset and address steps are performed for all Y electrodelines Y₁, Y₂, . . . Y₄₈₀, during a certain period and a displaydischarge step is then performed.

[0010] Referring to FIG. 4, a unit frame is divided into 8 subfieldsSF₁, SF₂, . . . SF₈ for achieving a time-divisional gray scale display.In each subfield, reset, address and display discharge steps areperformed, and the time allocated to each subfield is determined by adisplay discharge time. For example, in the case of displaying 256scales by 8-bit video data in the unit of frames, if a unit frame(generally {fraction (1/60)} second) comprises 256 unit times, the firstsubfield SF₁, driven by the least significant bit (LSB) video data, has1 (2⁰) unit time, the second subfield SF₂ 2 (2¹) unit times, the thirdsubfield SF₃ 4 (2²) unit times, the fourth subfield SF₄ 8 (2³) unittimes, the fifth subfield SF₅ 16 (2⁴) unit times, the sixth subfield SF₆32 (2⁵) unit times, the seventh subfield SF₇ 64 (2⁶) unit times, and theeighth subfield SF₈, driven by the most significant bit (MSB) videodata, 128 (2⁶) unit times. In other words, since the sum of unit timesallocated to the respective subfields is 257 unit times, 255 scales canbe displayed, 256 scales including one scale which is notdisplay-discharged at any subfield.

[0011] In the driving method of the multiple address overlappingdisplay, a plurality of subfields SF₁, SF₂, . . . SF₈ are alternatelyallocated in a unit frame. Thus, the time for a unit subfield equals thetime for a unit frame. Also, the elapsed time of all unit subfields SF₁,SF₂, . . . SF₈ is equal to the time for a unit frame. The respectivesubfields overlap on the basis of the driven Y electrode lines Y₁, Y₂, .. . Y₄₈₀, to form a unit frame. Thus, since all subfields SF₁, SF₂, . .. SF₈ exist in every timing, time slots for addressing depending on thenumber of subfields are set between pulses for display discharging, forthe purpose of performing the respective address steps.

[0012]FIG. 5 shows an electrode line pattern of the general plasmadisplay panel 1 driven based on the address-display separation drivingmethod. Referring to FIG. 5, in the general plasma display panel basedon the address-display separation driving method, each of the addresselectrode lines A₁, A₂, . . . A_(m) is cut in a middle portion to forman upper panel and a lower panel. A first Y electrode line Y₁ to an$\frac{n}{2}$

[0013] th Y electrode line $Y_{\frac{n}{2}}$

[0014] and a first X electrode line X₁ to an $\frac{n}{2}$

[0015] th X electrode line $X_{\frac{n}{2}}$

[0016] are allocated to the upper panel. An$\left( {\frac{n}{2} + 1} \right)$

[0017] th Y electrode line to an nth Y electrode line Y₁ and a$\left( {\frac{n}{2} + 1} \right)$

[0018] th X electrode line $X_{\frac{n}{2} + 1}$

[0019] to an nth X electrode line X_(n) are allocated to the lowerpanel. As described above, since the plasma display panel 1 is separatedinto two parts to then be simultaneously driven, an addressing time isreduced to a half.

[0020] In order to drive the separately driven plasma display panelshown in FIG. 5 by the address-display overlapping driving method shownin FIG. 4, a driving method in which the minimum driving periodconsisting of a minimum display discharge period, a minimum resetperiod, and a minimum address period is consistently repeated, isgenerally used. According to this driving method, the pulses for displaydischarges are alternately applied to all Y and X electrode lines duringthe minimum display discharge period, and the minimum reset and addressperiods are applied between the minimum display discharge periods. Inother words, the minimum reset and address periods are applied duringthe quiescent period of a sustained discharge. Here, during the minimumaddress period, the scan pulses are applied to at least one Y electrodeline in the order of the respective subfields SF₁, SF₂, . . . SF₈, andthe corresponding display data signals are applied to the respectiveaddress electrode lines.

[0021] When the above-described driving method is adopted to theseparately driven plasma display panel, the phase of the minimum drivingperiod of the upper panel has been conventionally equal to that of thelower panel. Accordingly, since the upper and lower panels have thedriving period of the same mode at the time, the overall maximuminstantaneous power becomes increased. For example, if all display cellsof the upper and lower panel emit light during the minimum displaydischarge period, the overall instantaneous power is considerablyincreased. Due to the considerable increase in the maximum instantaneouspower, the burden in the capacity of a power supply circuit and theeffects of noise and electromagnetic interference are also increased.

SUMMARY OF THE INVENTION

[0022] To solve the above problem, it is an object of the presentinvention to provide a method of driving a plasma display panel whichcan reduce the burden on the capacity of a power supply circuit and theeffects of noise and electromagnetic interference.

[0023] Additional objects and advantages of the invention will be setforth in part in the description which follows and, in part, will beobvious from the description, or may be learned by practice of theinvention.

[0024] To achieve the above and other objects of the invention, there isprovided a method of driving a plasma display panel having address linescut into two parts to form first and second panels which are separatelydriven, the method comprising generating driving periods of differentmodes at any given time for the first and second panels.

[0025] To achieve the above and other objects of the invention, there isalso provided a method of driving a plasma display panel having addresslines cut into two parts to form first and second panels which areseparately driven, the method comprising temporally alternating minimumdisplay discharge periods for each of the first and second panels.

[0026] To achieve the above and other objects of the invention, there isstill also provided a method of driving a plasma display panel havingfront and rear substrates opposed to and facing each other, X and Yelectrode lines formed between the front and rear substrates to beparallel to each other, address electrode lines formed to be orthogonalto the X and Y electrode lines, to define corresponding pixels atinterconnections, and the address electrode lines are cut into two partsat the middle portions thereof to then form first and second panelsseparately driven such that the minimum driving period includes adisplay discharge period, a reset period and an address period, a scanpulse is applied to at least one of the respective Y electrode linesduring the address period and the corresponding display data signals aresimultaneously applied to the respective address electrode lines to formwall charges at pixels to be displayed, pulses for a display dischargeare alternately applied to the X and Y electrode lines to cause adisplay discharge at the pixels where the wall charges have been formed,and a reset pulse for forming space charges while erasing the wallcharges remaining from the previous subfield is applied to thecorresponding Y electrode lines during the reset period, wherein theaddress period is applied to the second panel while the displaydischarge period and the reset period is applied to the first panel.

[0027] Accordingly, since the upper panel and the lower panel havedriving periods of different modes all the time, the maximuminstantaneous power is relatively decreased. For example, for alldisplay cells of the upper and lower panels, the minium displaydischarge periods alternate temporally. Thus, the overall instantaneouspower is relatively decreased. Therefore, the burden in the capacity ofa power supply circuit and the effects of noise and electromagneticinterference can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above objects and advantages of the present invention willbecome more apparent by describing in detail a preferred embodimentthereof with reference to the attached drawings in which:

[0029]FIG. 1 shows an internal perspective view illustrating thestructure of a general three-electrode surface-discharge plasma displaypanel;

[0030]FIG. 2 shows an electrode line pattern of the plasma display panelshown in FIG. 1;

[0031]FIG. 3 is a cross section of an example of a pixel of the plasmadisplay panel shown in FIG. 1;

[0032]FIG. 4 is a timing diagram showing the format of a unit displayperiod based on a general method for driving the plasma display panelshown in FIG. 1;

[0033]FIG. 5 is a diagram showing an electrode line pattern of a generalplasma display panel based on an address-display separation drivingmethod; and

[0034]FIG. 6 is a voltage waveform diagram of driving signals in a unitdisplay period based on a method of driving a plasma display panelaccording to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0035]FIGS. 6A through 6C show driving signals in a unit subfield basedon a driving method according to an embodiment of the present invention.In FIGS. 6A through 6C, reference marks S_(Y1), S_(Y2), . . . S_(Y4)(FIGS. 6A through 6D) denote upper Y electrode driving signals appliedto upper Y electrode lines corresponding to first through fourthsubfields SF₁, SF₂, . . . SF₄ of FIG. 4, and$S_{{Y\frac{n}{2}} + 1},S_{{Y\frac{n}{2}} + 2},\quad {{\dddot{}}\quad S_{{Y\frac{n}{2}} + 4}}$

[0036] (FIGS. 6E through 6H) denote lower Y electrode driving signalsapplied to the respective lower Y electrode lines. In more detail,S_(Y1) denotes a driving signal applied to an upper Y electrode line ofthe first subfield SF₁, S_(Y2) denotes a driving signal applied to anupper Y electrode line of the second subfield SF₂, S_(Y3) denotes adriving signal applied to an upper Y electrode line of the thirdsubfield SF₃, S_(Y4) denotes a driving signal applied to an upper Yelectrode line of the fourth subfield SF₄, $S_{{Y\frac{n}{2}} + 1}$

[0037] denotes a driving signal applied to a lower Y electrode line ofthe first subfield SF₁, $S_{{Y\frac{n}{2}} + 2}$

[0038] denotes a driving signal applied to a lower Y electrode line ofthe second subfield SF₂, $S_{{Y\frac{n}{2}} + 3}$

[0039] denotes a driving signal applied to a lower Y electrode line ofthe third subfield SF₃, and $S_{{Y\frac{n}{2}} + 4}$

[0040] denotes a driving signal applied to a lower Y electrode lines ofthe fourth subfield SF₄, respectively. Reference mark S_(X1..4) (FIG.6I) denotes driving signals applied to upper X electrode line groupscorresponding to scanned upper Y electrode lines, and$S_{{X\frac{n}{2}} + {1\ldots \quad 4}}$

[0041] (FIG. 6J) denotes driving signals applied to the lower Xelectrode line groups corresponding to scanned lower Y electrode lines,S_(UA1..m) (FIG. 6K) denotes upper display data signals corresponding toscanned upper Y electrode lines, S_(LA1..m) (FIG. 6L) denotes lowerdisplay data signals corresponding to scanned upper Y electrode lines,and GND denotes a ground voltage.

[0042] Although only four subfields are illustrated in FIGS. 6A through6L for brevity, the same driving method can also be applied to 8subfields. For example, the addressing period for the upper Y electrodelines corresponding to the fifth through eighth subfields SF₅, SF₆, . .. SF₈of FIG. 4 is T₄₂, and the addressing period for the lower Yelectrode lines is T₅₁.

[0043] Referring to FIGS. 6A through 6L, while the minimum displaydischarge periods and the minimum reset periods T₁₁, T₂₁, T₃₁, T₄₁, T₅₁,and T₆₁, are applied to the upper panel, the minimum address periods areapplied to the lower panel. Then, while the minimum address periods T₁₂,T₂₂, T₃₂, T₄₂, T₅₂ and T₆₂, are applied to the upper panel, the minimumdisplay discharge periods and the minimum reset periods are applied tothe lower panel. As described above, the upper panel and the lower panelhave driving periods of different modes all the time, and as a result,the overall maximum instantaneous power is relatively reduced. Forexample, if all the display cells of the upper and lower panels emitlight, since the minimum display discharge periods alternate temporally,the overall instantaneous power is relatively lowered. Accordingly, theburden in the capacity of a power supply circuit and the effects ofnoise and electromagnetic interference can be reduced.

[0044] During the respective display discharge periods, displaydischarges occur at pixels where wall charges have been formed, byalternately applying pulses 2 and 5 for display discharges to the X andY electrode lines X₁, X₂, . . . X_(n) and Y₁, Y₂, . . . Y₄₈₀. During therespective minimum reset periods, reset pulses 3 are applied to the Yelectrode lines to be scanned during subsequent address periods forforming space charges while erasing the wall charges remaining from theprevious subfield. During the minimum address periods, while scan pulses6 are sequentially applied to the Y electrode lines corresponding tofour subfields, the corresponding display data signals are applied tothe respective address electrode lines, thereby forming wall charges atpixels to be displayed.

[0045] Predetermined quiescent periods exist after application of thepulses 3 and before application of the scan pulses 6, to make spacecharges be distributed smoothly at the corresponding pixel areas. InFIG. 6, T₁₂, T₂₁, T₂₂ and T₃₁ are quiescent periods for the upper Yelectrode lines of the first through fourth subfields SF₁ through SF₄,and T₂₁, T₂₂, T₃₁ and T₃₂ are quiescent periods for the lower Yelectrode lines of the first through fourth subfields SF₁ through SF₄.Although the pulses 5 for display discharges applied during therespective quiescent periods cannot actually cause a display discharge,they allow space charges to be distributed smoothly at the correspondingpixel areas. However, the pulses 2 for display discharges applied duringnon-quiescent periods cause display discharges to occur at the pixelswhere the wall charges have been formed by the scan pulses 6 and thedisplay data signals S_(UA1..m) or S_(LA1..m).

[0046] During the minimum address period T₃₂ or T₄₁ between the finalpulses among the pulses 5 for display discharge applied during thequiescent periods and the first subsequent pulses 2, addressing isperformed four times. For example, during the period T₃₂, addressing isperformed for the corresponding upper Y electrode lines of the firstthrough fourth subfields SF₁ through SF₄. Also, during the period T₄₁,addressing is performed for the corresponding lower Y electrode lines ofthe first through fourth subfields SF₁ through SF₄. As described abovewith reference to FIG. 4, since all subfields SF₁, SF₂, . . . SF₈ existat every timing, time slots for addressing, depending on the number ofsubfields are set during the minimum address periods for the purpose ofperforming the respective address steps.

[0047] After the pulses 2 and 5 for display discharges simultaneouslyapplied to the Y electrode lines Y₁, Y₂, . . . Y_(n) terminate, thepulses 2 and 5 for display discharges simultaneously applied to thecorresponding electrode lines X₁, X₂, . . . X_(n) start to occur. Scanpulses 6 and the corresponding display data signals S_(UA1...m) orS_(LA1...m) are applied during the minimum address period before thepulses 2 and 5 for display discharges simultaneously applied to the Yelectrode lines Y₁, Y₂, . . . Y_(n) of the next minimum displaydischarge period start to occur after the pulses 2 and 5 for displaydischarges simultaneously applied to the electrode lines X₁, X₂, . . .X_(n) terminate.

[0048] As described above, since the upper panel and the lower panelhave driving periods of different modes all the time, the maximuminstantaneous power is relatively decreased. For example, for alldisplay cells of the upper and lower panels, the minium displaydischarge periods alternate temporally. Thus, the overall instantaneouspower is relatively decreased. Therefore, the burden in the capacity ofa power supply circuit and the effects of noise and electromagneticinterference can be reduced.

[0049] Although a few preferred embodiments of the present inventionhave been shown and described, it would be appreciated by those skilledin the art that changes may be made in this embodiment without departingfrom the principles and spirit of the invention, the scope of which isdefined in the claims and their equivalents.

What is claimed is:
 1. A method of driving a plasma display panel havingaddress lines cut into two parts to form first and second panels whichare separately driven, the method comprising: generating driving periodsof different modes at any given time for the first and second panels, byapplying a minimum display discharge period and a minimum reset periodto the first panel while applying a minimum address period to the secondpanel.
 2. A method of driving a plasma display panel having front andrear substrates opposed to and facing each other, X and Y electrodelines formed between the front and rear substrates to be parallel toeach other, address electrode lines formed to be orthogonal to the X andY electrode lines, to define corresponding pixels at interconnections,and the address electrode lines are cut into two parts at the middleportions thereof to then form first and second panels separately drivensuch that the minimum driving period includes a display dischargeperiod, a reset period and an address period, a scan pulse is applied toat least one of the respective Y electrode lines during the addressperiod and corresponding display data signals are simultaneously appliedto the respective address electrode lines to form wall charges at pixelsto be displayed, pulses for a display discharge are alternately appliedto the X and Y electrode lines to cause a display discharge at thepixels where the wall charges have been formed, and a reset pulse forforming space charges while erasing the wall charges remaining from aprevious subfield is applied to the corresponding Y electrode linesduring the reset period, wherein the driving method comprises: applyingthe address period to the second panel while applying the displaydischarge period and the reset period to the first panel.